1. Field
The present disclosure pertains to transmitting and/or encoding a clock signal within cycles of a multi-signal data transfer.
2. Background
Various standards have been promulgated for data transfer. In one example, the Mobile Industry Processor Interface (MIPIO) Alliance has defined a High-speed Synchronous Serial Interface (HSI) Specification, MIPI DPHY Low Power (LP) signaling for use in single-ended signaling that employs, for example, a synchronous complementary metal-oxide-semiconductor (CMOS) (push-pull) communication interface. Data transfer schemes often use a dedicated clock or strobe signal line to send cycle timing information from a transmitter device to a receiver device.
The use of a dedicated clock or strobe signal line requires using at least one additional conductor. For single-rate signaling applications, one data symbol per one full clock period (clock high and clock low) is sent. The maximum data rate is often limited by a maximum allowed frequency of the clock line of the system rather than maximum allowed frequency of the data line. The maximum data rate is also often limited by skew between clock and data that may be hard to control to be optimal.
Therefore, an efficient way to embed a clock signal within a multi-wire single-ended signaling system is needed.